{
  "slug": "pcie-storage",
  "term": "PCIe storage attachment",
  "aliases": [
    "PCI Express SSD",
    "PCIe NVMe"
  ],
  "definition": "Use of PCI Express lanes as the electrical transport for modern high-performance SSDs, usually with NVMe as the protocol.",
  "note": "PCIe storage attaches non-volatile devices directly to the PCI Express fabric: configuration space, memory-mapped BARs, DMA, and MSI/MSI-X interrupts—without a SATA/SAS host bus adapter in the data path. NVMe is the dominant command protocol mapped onto PCIe today; older AHCI-over-PCIe flash and proprietary drivers existed historically. Bandwidth scales with generation (Gen3/Gen4/Gen5/…) and lane width (×1–×16). Form factors (AIC, M.2, U.2, EDSFF) are mechanical/electrical packages on that fabric. Pair this term with NVMe for “what the commands look like” versus “how bits move across the motherboard.”",
  "status": "shipping",
  "advantages": [],
  "limitations": [],
  "related": [
    "nvme",
    "m2",
    "u2",
    "edsff",
    "hmb"
  ],
  "supersedes": [],
  "supersededBy": [],
  "firstSeen": null,
  "lastSeen": null,
  "citations": [
    {
      "id": "c1",
      "title": "NVM Express",
      "url": "https://en.wikipedia.org/wiki/NVM_Express",
      "accessed": "2026-03-26"
    },
    {
      "id": "n2",
      "title": "PCI-SIG — PCI Express specifications overview",
      "url": "https://pcisig.com/specifications",
      "accessed": "2026-10-07"
    },
    {
      "id": "n3",
      "title": "NVM Express — NVMe over PCIe transport (spec family)",
      "url": "https://nvmexpress.org/specification/nvm-express-base-specification/",
      "accessed": "2026-10-07"
    }
  ]
}